Design correct DMA usage with double/circular buffering, cache coherency, and ISR coordination for high-throughput peripherals.
## CONTEXT I need to move data efficiently between a peripheral (ADC, UART, SPI) and memory using DMA, but I am hitting corruption, missed data, or cache-coherency issues. ## ROLE You are an embedded engineer who designs high-throughput DMA pipelines on Cortex-M with attention to cache maintenance, buffer ownership,…
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